1. Field of the Invention
The present invention relates to a level shifter.
2. Description of the Related Art
In advanced IC design, the core logic and the I/O unit are powered by different voltage sources.
For example, in a 0.13 um process, the core logic is generally powered by a voltage source of 1.2V while the I/O unit is generally powered by another voltage source of 3.3V. Because the core logic works to be within a range of a first voltage range (e.g. 0-1.2V) and the I/O unit works to be within a range of a second voltage range (e.g. 0-3.3V), a level shifter is required between the core logic and the I/O unit to propagate signals correctly.
FIG. 1 depicts a conventional level shifter. The level shifter 100 comprises two inverters Inv1 and Inv2, a differential input pair 102 and a cross coupled pair 104. The input signal IN works to be within a range of a first voltage range. A first voltage source VDD that determines the first voltage range is operative to power both of the inverters Inv1 and Inv2. The inverters Inv1 and Inv2 output signals INb and IN′, respectively, to be received by the differential input pair 102. As shown, the differential input pair 102 and the cross coupled pair 104 are powered by a second voltage source VCC to generate an output signal OUT. The generated output signal OUT works to be within a range of a second voltage range determined by the second voltage source VCC. To sum up, the level shifter 100 converts the input signal IN (to be within a range of the first voltage range) into the output signal OUT (to be within a range of the second voltage range) for level shifting of the propagating signals between two units powered by distinct voltage sources.
The conventional level shifter 100, however, has to refer to the voltage source (i.e. the first voltage source VDD) of a preceding unit as well as the voltage source (i.e. the second voltage source VCC) of a succeeding unit, and contains transistors of various oxide thicknesses (depending on the voltage sources coupled thereto). Thus, additional design complexity is required. Furthermore, the conventional level shifter 100 uses a positive feedback design, which results in slow performance of the differential input pair 102 and the cross coupled pair 104 and there is a considerable delay between the input signal IN and the output signal OUT. Furthermore, the variations in the dimensions of the transistors of the differential input pair 102 or the cross coupled pair 104 may result in a considerable mismatch between the rising time and the falling time of the output signal OUT of the level shifter 100.
Thus, an accurate, high-transition speed and small-sized level shifter is called for.